Design engineer Empleos en Gresham or

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Job Description:

The Mixed Signal Development Group is responsible for delivering analog and mixed-signal IPs to product divisions within Microchip. We work with leading edge CMOS and FinFET processes to produce analog integrated circuits for wireline applications. We enable technology that allows Microchip’s products to interface to the outside world.

As a Mixed-Signal IP Technical Lead/Architect in the Mixed-Signal Development Group, you will be responsible for the end-to-end technical leadership of mixed-signal IPs—including IP licensing, integration, and silicon validation support—across a range of advanced SoC projects. Your focus will be on key analog and mixed-signal building blocks such as high-speed SERDES, PLLs, PVT sensors, IOs, and other critical IPs. You will collaborate closely with cross-functional teams to ensure successful delivery and integration of IPs into complex SoC designs.

Key Responsibilities:

• Define and review mixed-signal IP interface specifications, integration guidelines, and verification plans.
• Lead the evaluation, selection, and licensing of third-party and internally developed IPs for SoC projects.
• Collaborate with silicon IP vendors to customize IP solutions and finalize Statement of Work (SOW)
• Architect and drive the integration of mixed-signal IPs into SoC designs, ensuring optimal performance and compatibility.
• Review and sign off system level clocking needs to meet electrical compliance
• Collaborate with design, verification, physical design, and test engineering teams to resolve integration and validation issues.
• Maintain up-to-date knowledge of industry trends, standards, and best practices in mixed-signal IP development and integration.
• Oversee and participate in silicon validation, characterization, and debug of mixed-signal IPs post-fabrication.

Requirements/Qualifications:

Qualifications:

• Bachelor’s degree in electrical engineering or related field with strong analog/mixed-signal background and at least 10 years of experience in analog/mixed-signal IP design, integration, and validation for SoC applications, or a Master’s degree with at least 7.5 years of such experience.
• Strong understanding of SoC architecture, digital-analog interfaces, and system-level integration challenges.
• Proven expertise in PLLs, high-speed SERDES, PVT sensors, IOs, and other analog building blocks.
• Familiarity with industry-standard EDA tools for design, simulation, and verification.
• Experience working with PCIe, SAS, SATA and Ethernet protocols is a plus
• Experience working with Chiplet technologies is a plus
• Possess understanding of device physics and basic ESD/Latch-up concepts
• Strong written and oral communication skills
• Excellent problem-solving, and leadership skills.
• Ability to work in a team environment
• Ability to quickly ramp on new projects

Travel Time:

0% - 25%

Physical Attributes:

Hearing, Seeing, Talking, Works Alone, Works Around Others

Physical Requirements:

80% sitting, 10% standing, 10% walking, 100% inside

Pay Range:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature. Find more information about all our benefits at the link below:The annual base salary range for this position, which could be performed in the US, is $75,000 - $232,000.*

*Range is dependent on numerous factors including job location, skills and experience.

Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.

For more information on applicable equal employment regulations, please refer to the .

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