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We are seeking a PCIe Validation & Emulation Engineer in San Jose, CA .
Title : PCIe Validation & Emulation Engineer
Location : San Jose, CA
Duration : Long Term Contract
Responsibilities :
- Create and document PCIe validation test plans, test cases, and scripts.
- Perform compliance testing to ensure adherence to PCIe standards.
- Identify and resolve performance bottlenecks within the PCIe interface.
- Collaborate with hardware and software design teams and other stakeholders to ensure successful integration and validation of PCIe subsystems.
Key Skills :
PCIe 4.0, 5.0, 6.0, C / C++, IOMMU, RISC V, x86-64 architecture, accelerators, Oscilloscope, Multimeter, Logic Analyzer, performance benchmarks.
Qualifications :
Strong knowledge of PCIe Architecture, Validation, and Debugging.Experience with PCIe BAR and IOMMU architecture.Developing critical components of EAI Firmware for inference deployment on EAI processors.Advanced programming skills in C / C++ for OS kernel and systems development.Understanding of RISC-V architecture is a plus.Deep understanding of OS concepts, data structures, x86-64, and accelerator architectures.Experience analyzing and tuning system performance benchmarks.Proficiency with low-level debug tools, emulators, and simulators.Excellent understanding of computer architecture and OS memory management concepts.Hardware debug skills : Oscilloscope, Multimeter, Logic Analyzer.Seniority level
Mid-Senior levelEmployment type
ContractJob industry
Semiconductor Manufacturing#J-18808-Ljbffr