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Design Verification Engineer
Design Verification EngineerApple • San Francisco, California, United States
Design Verification Engineer

Design Verification Engineer

Apple • San Francisco, California, United States
Hace 9 días
Tipo de contrato
  • A tiempo completo
Descripción del trabajo

Overview

At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet and changing the game? We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers daily. This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to : establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.

Responsibilities

Study design specification and create test plan

Develop infrastructure in SystemVerilog / UVM to stress the design

Develop and fix failures from regressions, close bugs

Use LLMs to do verification efficiently

Preferred Qualifications

Deep knowledge of OOP, SystemVerilog and UVM

Deep knowledge in developing scalable and portable test-benches

Strong experience with verification methodologies and tools such as simulators, waveform viewers, Build and run automation, coverage collection, gate level simulations

Working experience using LLMs for efficiency and quality

Experience with power-aware (UPF) or similar verification methodology

Excellent knowledge of one of the scripting languages such as Python, Perl, TCL

Experience with serial protocols such as PCIe or USB, parallel protocol such as DDR is a plus but not required

Knowledge of formal verification methodology is a plus but not required

Knowledge of emulation for verification technologies is a plus but not required

Pay & Benefits

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $181,100 and $318,400, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including : Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.

Note : Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.

Apple accepts applications to this posting on an ongoing basis.

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Design Verification Engineer • San Francisco, California, United States

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