Responsibilities
· Develop test plans, tests and verification infrastructure for complex Block level / IP / Sub-system.
· Create verification environment using SV and UVM methodology.
· Create reusable bus functional models, monitors, checkers and scoreboards.
· Drive functional coverage driven verification closure.
· Work with the rest of the design team on design verification, debugging and bug resolution
Qualifications
· Bachelor's degree in Electronics Engineering, Electrical Engineering, or Computer Engineering
· 0-2 years of verification experience
· Good understanding of digital design concepts
· Good understanding of C/C++ or any OOP based programming language
· Exposure to Verilog/SystemVerilog or VHDL language
· Exposure to HVL-based verification with expertise in SV & OVM/UVM would be an asset
· Good analytical problem solving
· Highly motivated to learn protocols, verification flow and methodology
· Good verbal and written communication skills
· Knowledge of scripting languages and Linux/Unix environment would be an asset
About Rambus
Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of
high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrow’s systems.
AMTS Verification Engineering • St-Pierre Street, Suite , Montreal, Canada, HY M
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