FPGA Developer

divh2Senior Fpga Design Engineer / h2pWe are seeking an experienced Senior Fpga Design Engineer with strong expertise in Rtl Development, Systemverilog / Vhdl, And Python To Support High-speed Networking And Mission-critical Systems In A Classified Environment. / ppThis Role Involves Designing Advanced Fpga Solutions, Developing Custom Ip, Integrating High-performance Interfaces, And Collaborating With Multidisciplinary Teams To Deliver Secure, High-reliability Products. / ppKey Responsibilities / pulliDesign, develop, and implement Rtl for high-speed networking applications. / liliCreate custom Ip cores and integrate third-party Ip into complex Fpga designs. / liliDefine and implement timing constraints, ensuring full timing closure on high-performance designs. / liliCollaborate closely with hardware and software engineers in a classified environment. / liliSupport verification, validation, and debugging activities throughout the design lifecycle. / liliOversee Fpga implementation, synthesis, place-and-route, and optimization for performance, area, and power. / li / ulpRequired Qualifications / pulliBachelors degree in Electrical Engineering, Computer Engineering, or related field. / lili7+ years of hands-on Fpga development experience. / liliStrong proficiency in Systemverilog and / or Vhdl. / liliDemonstrated experience with Xilinx and / or Intel Fpga design tools (Vivado, Quartus, etc.). / liliExperience with high-speed interfaces such as PCIe, Ethernet, DDR, and similar technologies. / liliProficiency in Python for automation, scripting, or design support tasks. / liliActive TS / SCI security clearance (required). / li / ulpDesired Skills / pulliExperience developing Fpga solutions for network security applications. / liliFamiliarity with networking standards, switching, routing, or packet-processing architectures. / liliExperience with scripting languages such as Python and Tcl for design automation and workflow optimization. / liliUnderstanding of hardware security principles, anti-tamper measures, or secure Fpga architectures. / li / ul / div