Verification engineer Jobs in Santa Clara, CA
Last updated: 1 day ago
Santa Clara (Remote candidates in the PST and MST time zones).Developing UVM based verification frameworks and testbenches, processes and flows.
Good understanding and hands-on experience in the UVM...Show moreLast updated: 1 day ago
Acceler8 Talent has partnered with a well-supported data center acceleration company that is actively searching for a driven.
This company is deeply committed to developing a novel interconnect arch...Show moreLast updated: 22 days ago
Triple Crown is a leading provider of hardware, embedded, software, and mechanical engineering talent.Businesses and technology teams, from Fortune 500 enterprises to emerging startups, rely on our...Show moreLast updated: 2 days ago
We are seeking a skilled and proactive Design Verification Engineer to join our team.The ideal candidate will have a strong background in product design, from concept to production, with proven exp...Show moreLast updated: 15 days ago
Job DescriptionJob Description.Reviewing the product designs and noting likely points of failure.Designing verification methodology based on product designs and failure points.Determining testing e...Show moreLast updated: 1 day ago
Job Title : Physical Verification Engineer.Base Compensation is $150K - $220K.ASICSoft is seeking an experienced.Physical Verification Engineer.
The ideal candidate will have hands-on expertise in.Ca...Show moreLast updated: 17 days ago
If you are a first time user, please create your candidate login account before you apply for a job.If you already have a Candidate Account, please Sign-In before you apply.Functional verification ...Show moreLast updated: 15 days ago
The focus of this role is to plan, build, and execute the verification of new and existing features for our custom silicon / ASIC designs, resulting in zero bugs in the final design to ensure first t...Show moreLast updated: 4 days ago
Role : Design Verification Engineer.Location : Sunnyvale, CA or Redmond, WA.Design Verification Engineering Services.Testbench development – System Verilog Universal Methodology (“UVM”), Python, and ...Show moreLast updated: 4 days ago
Reviewing the product designs and noting likely points of failure.Designing verification methodology based on product designs and failure points.
Determining testing environments and verification to...Show moreLast updated: 1 day ago
Pay Rate : $89 - $100 hourly on W2.Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified.
Build test plan documentation, accounting for...Show moreLast updated: 1 day ago
Location : USA-CA San Jose Innovation Drive.Formal and functional verification of complex designs, especially around external interfacing IPs.
Identify designs that are suitable for formal verificati...Show moreLast updated: 30+ days ago
Cupertino,California,United States.Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies ...Show moreLast updated: 15 days ago
ASIC Design Verification Engineer.Sunnyvale, California or Austin, Texas.Job Description & Skill Requirement.Define and implement IP / SoC verification plans, build verification test benches to enabl...Show moreLast updated: 30+ days ago
ASIC Design Verification Engineer.Sunnyvale, California or Austin, Texas.Job Description & Skill Requirement.Define and implement IP / SoC verification plans, build verification test benches to enabl...Show moreLast updated: 1 day ago
Years of 8+ years of experience.Design Verification Engineering Services.Testbench development – System Verilog Universal Methodology (“UVM”), Python, and C tests.
Integration / development of C tests...Show moreLast updated: 4 days ago
Physical Verification Engineer.We pride ourselves on our ability to connect talented professionals with leading-edge projects that shape the future of technology.
We are excited to offer a unique op...Show moreLast updated: 19 days ago
The application window has been extended and expected to close on 03 / 07 / 2025.The job posting may be removed earlier if the position is filled or if a sufficient number of applications are received....Show moreLast updated: 15 days ago
Design Verification Engineering Services.Testbench development - System Verilog Universal Methodology ("UVM"), Python, and C tests.
Integration / development of C tests / Application Programming Interfa...Show moreLast updated: 1 day ago
Develop test plans and verification infrastructure for low-power ASIC designs.Build verification environments using SV / UVM methodology.
Build reusable bus functional models, drivers, monitors, check...Show moreLast updated: 1 day ago
- Promoted
Design Verification Engineer
TPI Global Solutionssanta clara, CA, United StatesTemporary
- Promoted
Design Verification Engineer
Acceler8 TalentSanta Clara, CA, United StatesFull-time
- Promoted
Physical Verification Engineer
Triple CrownSan Jose, CA, United StatesFull-time
- Promoted
Design Verification Engineer
The Fountain GroupSanta Clara, CA, United States$72.59–$92.59 hourly
Full-time
- Promoted
ASIC Verification Engineer
ZipRecruiterSan Jose, CA, United States$85.00 hourly
Full-time
- Promoted
Physical Verification Engineer
ASICSoftSan Jose, CA, United States$150,000.00–$220,000.00 yearly
Full-time
- Promoted
Design Verification Engineer
Broadcom CorporationSan Jose, CA, United States$107,000.00–$171,000.00 yearly
Full-time
- Promoted
Design Verification Engineer
Quest GlobalSan Jose, CA, United StatesFull-time
- Promoted
Design Verification Engineer
Themesoft Inc.Sunnyvale, CA, United StatesFull-time +1
- Promoted
ASIC Verification Engineer
YohSan Jose, CA, United States$85.00 hourly
Full-time
- Promoted
Design Verification Engineer
LanceSoftSanta Clara, CA, United States$89.00–$100.00 hourly
Full-time
- Promoted
Design Verification Engineer
Broadcom Inc.San Jose, CA, United States$107,000.00–$171,000.00 yearly
- Promoted
Formal Verification Engineer
AppleCupertino, CA, United States$121,900.00–$183,600.00 yearly
Full-time
- Promoted
Design Verification Engineer
Intelliswift - An LTTS Companysanta clara, CA, United StatesFull-time
- Promoted
Design Verification Engineer
IntelliswiftSan Jose, CA, United StatesFull-time
- Promoted
Design Verification Engineer
Globex DigitalSunnyvale, CA, United StatesFull-time
- Promoted
Physical Verification Engineer
Sintegra Inc.San Jose, CA, United StatesFull-time
- Promoted
ASIC Verification Engineer
CiscoSan Jose, CA, United StatesFull-time
- Promoted
Design verification Engineer
Diverse LynxSunnyvale, CA, United StatesFull-time
- Promoted
Digital Verification Engineer
Ethan Alexander Group, Inc.Campbell, CA, United StatesFull-time
Design Verification Engineer
TPI Global Solutionssanta clara, CA, United States1 day ago
Job type
- Temporary
Job descriptionCollaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements Ideally Masters + 5 years or Bachelors + 8 years is preferred Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Good understanding and hands-on experience in the UVM concepts and System Verilog language Scripting language experience : Perl, Ruby, Makefile, shell preferred.
Staff Verification Engineer
12+ Months Contract
Santa Clara (Remote candidates in the PST and MST time zones)
Experience Required :
- Developing UVM based verification frameworks and testbenches, processes and flows
- Good understanding and hands-on experience in the UVM concepts and System Verilog language
Key Responsibilities :
Experience :