FPGA Hardware Engineer

Description

Leidos has a new and exciting opportunity for a FPGA Hardware Designer Engineer in our National Security Sector's (NSS) Cyber & Analytics Business Area (CABA) . Active TS / SCI with a polygraph is required. Our talented team is at the forefront in Security Engineering, Computer Network Operations (CNO), Mission Software, Analytical Methods and Modeling, Signals Intelligence (SIGINT), and Cryptographic Key Management. At Leidos , we offer competitive benefits , including Paid Time Off, 11 paid Holidays, 401K with a 6% company match and immediate vesting, Flexible Schedules, Discounted Stock Purchase Plans, Technical Upskilling, Education and Training Support, Parental Paid Leave, and much more. Join us and make a difference in National Security!

The FPGA Hardware Designer Engineer will support a high performing program consisting of a small team responsible for the full life cycle of the design, programming, and testing of next generation cryptographic communications security modules that serve as the standard protecting data on both critical US and foreign ally data links. This hands-on engineering work covers the full life cycle of hardware and software development, including requirements definition, design, implementation using FPGAs and embedded software, device testing and system integration support. The modules developed undergo Information Assurance certification documentation and testing prior to embedment in a variety of system applications including helicopters and UAVs.

Primary Responsibilities :

• Assisting with designing new products and processes and improving and maintaining existing products, Providing technical leadership to less experienced engineers.
• Communicating with the other engineering personnel to coordinate the interrelated design and assure project completion, Developing and maintain documentation for the P&R design flows.
• Conducting design analysis on components and assemblies to assist in the development process by ensuring designs are cost efficient, able to be manufactured, and reliable
• Applying ASIC or FPGA place and route (P&R) tools with various libraries to create physical implementations of designs, Leading the designs of new products and processes and improve and maintain existing products
• Assisting with de-processing electronic components and retrieving stored firmware or software, Designing new products and processes and improving and maintaining existing products
• Working with tool and library vendors to develop solutions for designers' P&R design challenges
• Integrating new P&R tools, P&R tool updates, and ASIC or FPGA design libraries into Government's computer aided design environment, documents the use of those tools and libraries, and Assist other physical designers to successfully complete their specific P&R design tasks

Basic Qualifications :

Desired Experience :

Development of security products within the Cyber Intelligence field is highly sought

Original Posting : March 21, 2025

For U.S. Positions : While subject to change based on business needs, Leidos reasonably anticipates that this job requisition will remain open for at least 3 days with an anticipated close date of no earlier than 3 days after the original posting date as listed above.

Pay Range :

Pay Range $126,100.00 - $227,950.00

The Leidos pay range for this job level is a general guideline onlyand not a guarantee of compensation or salary. Additional factors considered in extending an offer include (but are not limited to) responsibilities of the job, education, experience, knowledge, skills, and abilities, as well as internal equity, alignment with market data, applicable bargaining agreement (if any), or other law.