FPGA Engineer

Human intuition. Machine intelligence. Relentless exploration.

Exceptional trading emerges where human intuition meets frictionless experimentation. Our platform and processes enable traders to rapidly investigate ideas, identify emergent patterns, and convert insights into live strategies. This synthesis creates a flywheel of discovery—the key to our pursuit of excellence.

The Role :

As an FPGA Engineer, you will operate at the absolute edge of performance, shaping our physical connection to global financial markets. You will be responsible for the entire lifecycle of our hardware acceleration solutions, from architectural design to in-system deployment. This is a role for an engineer who thrives on blurring the line between hardware and software—someone who can translate complex algorithms directly into silicon and write the performant C++ software that bridges the gap.

You are a systems thinker who understands that true optimization happens when hardware and software are designed in concert. You will have a direct and measurable impact on our trading performance by engineering solutions that execute with nanosecond precision.

Responsibilities :

• RTL Design and Implementation : Architect, implement, and verify high-performance, low-latency FPGA logic in SystemVerilog for market data processing, order execution, and other critical trading functions.
• Hardware / Software Co-Design : Develop the C++ drivers, APIs, and testing software required to create a seamless, high-bandwidth interface between our FPGAs and the main application running on the host CPU.
• System Integration and Bring-Up : Own the process of bringing up and debugging FPGA-based accelerator cards within our server environment. You'll work at the "card level" to ensure hardware is fully integrated and functioning correctly within the larger system.
• Achieve Timing Closure : Drive the synthesis, placement, and routing process to meet aggressive timing, resource, and power targets.
• Collaborate on System Architecture : Partner with C++ engineers and quantitative researchers to identify opportunities for hardware acceleration and co-design solutions that optimize the entire trading pipeline.

You Bring :

HDL Proficiency : Deep fluency in SystemVerilog or Verilog for complex, low-latency designs.

Intellectual Curiosity : You have a low ego and seek out the best ideas, regardless of their source.

We Offer :

At our firm, our people come first. We are committed to building a culture of collaboration, where we support each other through challenges and celebrate our collective successes. We believe that the strength of a modern workplace lies in its diverse workforce—diverse in ideas, cultures, and experiences. We actively foster this environment and take pride in being an equal opportunity employer. In compliance with New York City’s Pay Transparency Law, the anticipated base salary for this role ranges from $150,000 - $250,000 annually, plus performance bonus, and based on experience and qualifications. Please note, this range excludes other components of total compensation, such as bonuses.

We offer competitive compensation packages, company equity, 401k matching, gender-neutral parental leave, and comprehensive medical, dental, and vision insurance. While we value flexibility, we believe that in-person collaboration is key to solving complex challenges, which is why we require employees to be in the office 4 days a week. In-office perks include lunch stipends, fully stocked kitchens, happy hours, and a great location with amazing colleagues.

Our top priority is our people. We invest in a culture that promotes togetherness, helping each other through challenges and celebrating each other's successes. We believe that modern workplaces succeed by having diverse high-performance workforces — in ideas, in cultures, and in experiences. We put in the effort to make such a workplace a daily reality and are proud to be an equal opportunity employer.

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