Staff / Sr Staff, SoC Clock Design Engineer

Overview

Join to apply for the Staff / Sr Staff, SoC Clock Design Engineer role at Eridu AI .

This range is provided by Eridu AI. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range

$210,000.00 / yr - $270,000.00 / yr

About the company

Eridu AI is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate training and inference for large-scale AI models. Today’s AI performance is frequently limited by system-level bottlenecks. Eridu AI delivers multiple industry-first innovations across semiconductors, software, and systems to unlock greater GPU utilization, reduce capital and power costs, and maximize data center efficiency. The company’s solutions and value proposition have been validated by several leading hyperscalers.

The company is led by a veteran team of Silicon Valley executives and engineers with decades of experience in state-of-the-art semiconductors, optics, software, and systems, including serial entrepreneur Drew Perkins, co-founder of Infinera, Lightera, Gainspeed and Mojo Vision.

About the Role

We are seeking a highly experienced and motivated Clock Designer – Design Lead to drive the definition, architecture, and implementation of high-speed clock distribution networks for complex, large-scale SoC designs. This role is critical in ensuring high-performance, low-skew clocking solutions across multi-core, multi-module systems at advanced process nodes (7nm and below).

Key Responsibilities

• Lead the architecture definition and implementation of high-speed clock distribution networks in large-scale ICs.
• Define and manage clock architecture specifications, timing budgets, and design methodologies for SoC designs.
• Perform clock distribution design modeling, analysis, and implementation to meet aggressive timing and power targets.
• Drive post-silicon clock distribution characterization and debug, identifying performance bottlenecks and optimizing solutions.
• Develop cross-clock domain data transfer logic and ensure reliable synchronization across timing domains.
• Design and implement de-skew mechanisms and cross-clock domain communication protocols.
• Collaborate with physical design teams for optimal clock tree synthesis, floorplanning, and integration into SoC flows.
• Own the clocking solution from concept to tape-out, ensuring first-pass silicon success across multiple technology nodes.
• Build and evolve clocking design methodologies, ensuring robust, reusable, and scalable design practices.
• Support synthesis, STA, and integration teams with design constraints (SDC / CDC) and cross-domain timing closure.
• Participate in system-level architecture reviews and cross-functional discussions to drive overall design quality and performance.

Required Qualifications

Preferred Qualifications

Why Join Us?

At Eridu AI, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI networking solutions, transforming data center capabilities.

The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.

Seniority level

Employment type

Job function

#J-18808-Ljbffr