Design Verification Engineer

We are seeking a highly skilled Design Verification Engineer to join our advanced semiconductor design team in the Bay Area. The ideal candidate will have a strong background in SystemVerilog, UVM , and C / C++ programming , and be capable of driving complex verification tasks independently. This is an exciting opportunity to work on next-generation SoC and IP designs in a fast-paced, innovation-driven environment.

Key Responsibilities

• Develop, enhance, and execute verification plans for complex SoC / IP blocks.
• Design and maintain SystemVerilog-based testbenches using UVM methodology .
• Develop C / C++ models, transactors, or test components to support mixed-language simulation environments.
• Perform functional and coverage-based verification , ensuring design correctness and completeness.
• Work closely with RTL designers and architects to define verification strategies and close verification coverage.
• Debug issues across simulation environments and regression runs using industry-standard tools.
• Automate verification flows and contribute to continuous process improvement.

Must-Have Skills & Experience

Preferred Qualifications

Why Join Us

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