FPGA Design Engineer – Verification (Hybrid – Denver, CO)
FPGA Design Engineer Verification (Hybrid Denver, CO)
We are looking for an FPGA Design Engineer for a global aerospace company. In this role, you will support over 50 different programs and research and development (R&D) efforts.
Your work will affect technology across military space, civil space, commercial space, missiles, missile defense platforms, satellite surveillance platforms, deep space exploration, and manned flight missions.
This is a 5-month contract (extensions likely), 40-hour-per-week role (4-day 10-hour shifts per week), hybrid role at Denver, CO.
MUST be a US citizen.
This is a W-2 role as a Stage 4 Solutions employee. Health benefits and 401K are offered.
Responsibilities :
- Work with low SWaP, radiation-hardened, space-rated devices.
- Devise a unique verification plan for a given design.
- Use SystemVerilog and Universal Verification Methodology (UVM) to verify a design in a Linux-based high-performance computing environment.
- Develop requirements, and test cases, build test benches, generate reports, and document verification results.
- Work with an independent design team to document and resolve bugs found in the design.
- Support all aspects of ASIC and FPGA development, including architecture, design, and analysis.
- Support technical reviews, and be able to present to internal and external stakeholders.
Requirements :
- 9+ years of experience in the design of FPGA and / or ASIC devices.
- HDL programming experience with VHDL, Verilog, and / or SystemVerilog.
- Experience in the verification of FPGA and / or ASIC devices.
- Experience with modern verification methodologies such as UVM / OVM.
- Experience in ASIC / FPGA life cycle (architecture, design, simulation, verification, validation, integration & test).
- Experienced in scripting such as Perl, TCL, Python.
- Experience developing test cases based off given requirements.
- Experience building test benches for FPGA / ASIC designs to provide randomized stimulus.
- Experience identifying and implementing necessary test exclusions.
- Experience generating coverage reports (code and functional).
- Knowledge of space-grade / qualified FPGAs and ASICs.
- FPGA / ASIC design experience is a plus.
- Bachelor’s Degree.
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