CPU CDC / STA Engineer

Role Number : 200571969-3760

Summary

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want to join us in these pursuits? Join us to help deliver the next groundbreaking Apple product!

As a CPU CDC / STA Engineer, you will play a major role analyzing the design and driving fixes as well as developing, maintaining and improving our Lint, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC) and Static Timing Analysis (STA) constraints and methodology for our CPUs across multiple design sites.

Description

In this role, you will be :

• Responsible for developing, improving, and maintaining the CDC and RDC sign-offs for CPU designs
• Working with RTL and DV teams to recommend System Verilog assertions needed to support CDC / RDC / STA constraints and assumptions
• Responsible for developing, enhancing, and maintaining key STA checks and associated sign-offs for our CPUs
• Responsible for debugging vendor tool problems and collaborate with designers to help solve their problems
• Working closely with EDA vendor representatives to drive improvements and new methodologies
• Working closely with RTL, Verification, CAD, and Physical Design teams

Minimum Qualifications

Minimum BS and 3+ years of relevant industry experience

Scripting skills in Tcl or Perl

Experience in one or more of the following : Static Timing Analysis (STA), Clock-Domain Crossing (CDC), or Reset Domain Crossing (RDC) solutions

Experience in Verilog

Preferred Qualifications

Experience in SystemVerilog Assertions (SVA) and Design Verification (DV) Simulations

Knowledge in Spyglass, VC-Static, PrimeTime, or Meridian is a plus

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