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Design Verification EngineerITResource Hunter • San Jose, CA, United States
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Design Verification Engineer

Design Verification Engineer

ITResource Hunter • San Jose, CA, United States
27 days ago
Job type
  • Full-time
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Job description

Job Title: Design Verification Engineer/Senior Design Verification Engineer/Staff Design Verification Engineer/Principal Design Verification Engineer
Location: San Jose, CA (Onsite)
Job Type: Full-Time

Job Summary
We are seeking a Design Verification Engineer to join our Internal IP DV team. You will ensure the custom IPs powering our chips including systolic arrays, DMA engines, and NoCs are robust, high-performance, and silicon-ready. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges. You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack.

Key responsibilities

  • Develop and maintain UVM/SystemVerilog testbenches for high-performance IPs (compute arrays, DMAs, NoCs, memory subsystems).
  • Define and execute verification plans covering functional correctness, corner cases, concurrency, and performance bottlenecks.
  • Debug complex datapath and protocol issues in RTL and testbench environments.
  • Work closely with architects and designers to validate functionality and design intent.
  • Partner with SW, FW, and emulation teams to ensure end-to-end bring-up and debug coverage.
  • Contribute to reusable DV infrastructure, coverage models, and methodology improvements.

You may be a good fit if you have

  • Proficiency with UVM and System Verilog.
  • Strong debugging and problem-solving skills for complex digital designs.
  • Solid knowledge of computer architecture and digital design fundamentals.
  • Hands-on experience verifying datapaths, memory systems, interconnects, or high-throughput fabrics.

Strong candidates may also have experience with

  • Familiarity with System Verilog Assertions (SVA) and formal verification techniques.
  • Experience verifying systolic arrays, DMA engines, or NoC/AXI protocols.
  • Scripting skills (Python/Perl/TCL or similar) for automation, debug and regression flows.
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Design Verification Engineer • San Jose, CA, United States

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