Physical Verification Engineer (ASIC Design)

Title : Physical Verification Engineer (ASIC Design)

Location : Phoenix AZ

Hybrid : Weekly 3 days onsite 2 days Remote

Contract : 06 Months

Role Overview

As a Physical Verification Engineer you will be responsible for ensuring that ASIC

layouts meet all foundry design rules and manufacturing requirements. You will own the

sign-off verification process - performing DRC LVS ERC and other checks to ensure

design integrity manufacturability and compliance with foundry specifications. Working

closely with layout physical design and CAD teams youll help deliver clean tape-

out ready GDS data for complex SoC and ASIC designs.

Key Responsibilities

• Perform physical verification of full-chip and block-level layouts including :
• DRC (Design Rule Check)
• LVS (Layout vs. Schematic)
• ERC (Electrical Rule Check)
• Antenna checks Density checks and metal fill verification
• Debug and resolve DRC / LVS violations by collaborating with physical design
• layout and circuit design teams.
• Execute foundry sign-off checks using advanced process technology node (e.g. 5nm 7nm 16nm).Manage and maintain PV runsets verification scripts and rule decks provide by foundries.
• Automate repetitive tasks and improve verification efficiency using Tcl Python or Perl hierarchical verification flows (chip-level and block-level integration).
• Ensure compliance with electromigration (EM) IR drop and reliabilit requirements in conjunction with sign-off teams.
• Support tape-out preparation including GDS merging data integrity checks and final report generation.
• Collaborate with CAD and methodology teams to refine verification flows and integrate new EDA tools or rule decks.

Qualifications Education :

Experience :

Technical Skills :

Soft Skills

Preferred Experience (Nice to Have)

Key Skills

Arabic Speaking,Logistics Operations,Lecturing,Community Support,Gynaecology & Obstetrics,AC Maintenance

Employment Type : Full Time

Experience : years

Vacancy : 1