Qualifications : MS or higher degree in EE, CS or related fields,Experience requirements : Entry level positions : 0-2 years of experienceSenior and above level positions : a minimum of 2 years of experienceProficiency in System Verilog, Object Oriented Programming, Scripting LanguagesExperience in UVM developmentDetailed understanding of UVM methodology, flows and test-bench structuresBasic understanding of IEEE802.
11 PHY and MAC standardExperience in debugging designs of IP level (Wi-Fi Baseband, and MAC) or SOC levelGood communication and documentation skillsResponsibilities : Work with system architects, algorithm engineers, and RTL designers to define Wi-Fi AP chip verification requirements.
Architect and buildIP and system UVM verification environments.Create IP and system verification coverage plans, and generate test cases, based on the specification and review the plan with system architects and design engineersReport failures, participate in the debugging with various teams, and track bugsConduct verification regressions, analyze the results, and review with design teamsDevelop verification flows for code coverage and functional coverage for Baseband, MAC, and SOC
Design Verification Engineer
Work and liaison with other Design Verification teams within our customer sites to identify holes in the design verification flow and implement corrective action. Key knowledge should include such topics as: IP validation, Gate level verification, FPGA Validation, Emulation, Silicon Validation, Refe...
Wireless Design Verification Engineer
You'll also work closely with the design teams to review specifications and architecture, extract features, define verification plan & coverage model. Apple's growing wireless silicon development team is developing the next generation of wireless silicon! In this role, you'll be responsible for ASIC...
ASIC Engineer, Design Verification
Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage. Develop and drive continuous Design Verification impr...
Design Verification Engineer
As a Design Verification Engineer in our team, you are at the center of the verification effort within our silicon design group! You will be designing and productizing state-of-the-art cellular baseband modems and RF link controllers targeted for SOCs. You are responsible for high quality verificati...
Hardware Design Verification and Performance Modeling Engineers
Design Verification engineer with a strong background in building testbenches and writing test sequences for complex IPs. My client can be described as "Developing Foundational Technologies for Chiplet Based Semiconductor Design". Work with design teams test plans, failure debug, coverage etc. ...
Design Verification Engineer - 24-01314
Title: Design Verification Engineer (GPU). As a GPU Design Verification Engineer, your talents will ensure the quality at the heart of our GPU architecture. BS in Computer Engineering, BSEE or comparable and 5+ years of industry experience in a design verification role. Work with architects and desi...
Principal IC Design Verification Engineer (500-700k pkg)
Principal IC Design Verification Engineer (500-700k pkg). Verification of complex switch designs and creating SystemVerilog based verification environments. Design Verification experience. Creating and executing test plans for RTL and gatesim based designs at both chip and block levels. ...
AI Design Verification Engineer
The focus of this role is to plan, build, and execute the verification of new and existing features for AMD's graphics processor IP, resulting in no bugs in the final design. You have a passion for modern, complex processor architecture, digital design, and verification in general. Collaborate with ...
Sr. Design Verification Engineer
Our Portland office is looking for enthusiastic engineers to join the CPU/IP/SoC verification team. Working closely with the local design team, you will be responsible for verifying subsystems such as caches, memories, and interconnects, as well as their integration into the larger SoC. We are looki...
FPGA Soft IP Design Verification Lead Engineer
As Lead DV Engineer focusing on IP Verification and Validation, you will be responsible for carrying out design validation for Intel's next generation IPs across the Intel FPGA IP product portfolios. BS/MS in Electrical Engineering, Computer Engineering or a closely related field of study plus 8 yea...