Performance Modeling / Verification Engineer - Intermediate (US)
ObjectWin TechnologySanta Clara, CA, United States2 days ago
Job type
- Full-time
Job descriptionB.E / M.E / M.Tech or B.S / M.S in EE / CSE with over 5 years of recent hands-on experience in SystemC and TLM2 modeling Proficiency in C / C++ programming. Understanding of memory controller architectures, including DDR, LPDDR, and other relevant standards is preferred. UVM verification experience is preferred. Experience with debuggers and handling complex projects. Experience working in geographically dispersed teams; must be a strong team player. Knowledge of system-level architecture including buses like AXI / AHB and bridges is a plus. Familiarity with version control systems such as Perforce or Git.
Bill Rate Range :
- (Negotiable to right candidate)
Preference is Hybrid but Open to a fully remote candidate.
Interview : 1hr long interview with Sr. Engineer in India.
JOB DUTIES :
Develop, enhance, and maintain SystemC / TLM2 models for memory controllers, peripherals, and interconnects, ensuring they accurately simulate the behavior and performance characteristics of the hardware.
Collaborate with cross teams to integrate models into AMD tools used for system-level designs, ensuring proper functionality and performance.
Identify bottlenecks and performance issues within models and work to optimize their performance to meet design specifications.
Develop and execute testbenches to validate the functionality and correctness of models, as well as participate in system-level testing and debugging.
Create clear and comprehensive documentation for models, including usage guidelines and design specifications.
Deliverables :
Cycle approximate performance models
SV / UVM Functional and Performance Verification
EXPERIENCE AND EDUCATION :
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Performance Engineer • Santa Clara, CA, United States
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