Technical Lead Design Verification Engineer
San Jose, CA
Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com .
We are looking for Senior Design Verification Engineers with a flair for being a code breaker and the ability to develop hybrid verification mechanisms for complex ASICs. Experience with SystemVerilog, C, C++, Python, or other scripting languages is a plus. Using your coding and problem-solving skills, you will contribute to the functional verification of the designs. You'll be responsible for the full verification lifecycle, from planning to writing tests, debugging, collecting, and closing coverage. You will also collaborate with software and system validation teams to develop and execute test plans on emulation platforms.
Required Experience
Preferred Experience
The base salary range is USD 147,000.00 – USD 195,000.00. Salary will be determined based on location, experience, and internal pay scales.
We value diversity and inclusion and encourage applicants from all backgrounds, including people of color, LGBTQ+ and non-binary individuals, veterans, parents, and persons with disabilities, to apply.
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Lead Design Engineer • San Jose, CA, United States