Senior Technical Staff Engineer - Design for Test

Senior Technical Staff Engineer - Design for Test

Company Description

Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Job Description

The DFT lead works in close partnership with different teams within the FPGA business unit spanning architecture, ASIC design, verification, physical implementation, and test engineering to implement the testability features into the combined FPGA and ASIC SOC. The DFT lead will be involved from the initial investigation and feasibility to tape-out, as well as silicon validation and characterization of test methods on Automatic Test Equipment (ATE).

Responsibilities

Manage DFT requirements across architecture, design, and product teams to ensure coverage, die cost, test cost and DFT integration requirements are met at the block and full chip level.

Define, implement and validate DFT features at the FPGA full chip and sub-systems level.

Collaborate closely with cross functional teams to support DFT insertion, synthesis, scan insertion, place-and-route, static timing analysis, timing closure, power analysis during test and quantifying full chip test coverage.

Establish and maintain DFT design and insertion guidelines and documents best practices for all development teams to follow.

Be current with emerging technologies and methodologies in DFT and incorporate them into the FPGA to continuously improve test cost and quality.

Work with Test and Product engineers to support development of firmware targeted test patterns, ATPG and mBIST test feature validation processes, and silicon debug activities.

Communicate project status and progress to chip lead and engineering management.

Qualifications

15+ years of DFT engineering experience through DFT pre and post silicon cycles.

Experience in creating and implementing complex FPGA / SoC DFT architecture in advanced technology nodes.

Expert level knowledge about IJTAG and JTAG test access, Streaming Scan Network (SSN), scan compression and insertion, SAF / TDF / PDF ATPG, memory BIST and repair, logic BIST, MISRs, at-speed testing of SoC / FPGA, fault simulation, quantifying full chip test coverage, DFT mode timing constraints and power control during test.

Familiar with DFT verification, silicon debug, memory and scan diagnostics.

Experience in PHY, high-speed IO, digital communication and functional test development.

Good understanding of Verilog, synthesis, physical implementation and STA.

Good understanding of verification methodology.

Preferred Skills and Experience

Knowledge of FPGA design flow is a plus.

Knowledge of embedded design and firmware methodology is a plus.

Understanding Arm or RISC IP’s, high speed interfaces such as PAM4 SerDes, DDR4 / 5, etc. is a plus.

Experience in leading multiple FPGA / SoC projects.

Travel Time

0% - 25%

Physical Attributes

Feeling, Handling, Hearing, Other, Seeing, Supervises Others, Talking, Works Alone, Works Around Others

Physical Requirements

10% walking, 10% standing, 80% sitting; 100% in doors; Usual business hours

Pay Range

We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature. Find more information about all our benefits at the link below : The annual base salary range for this position, which could be performed in California, is $88,000 - $232,000.

• Range is dependent on numerous factors including job location, skills and experience.

EEO Statement

Microchip Technology Inc is an equal opportunity / affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.

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