Physical Design Engineer

Job Title

Static Timing Analysis (STA) Engineer

Responsibilities

• Full chip and Block constraints development and constraints generation.
• Full chip and Block Synthesis, STA and timing closure using Primetime and DMSA flow.
• Run and debug Formality and VCLP Tools.
• Interfacing with internal external teams including Design, IP, Library.
• Methodology & Flow development of Synthesis , Formality, STA & Timing Closure .
• Working independently with the PNR & RTL design team on Physical implementation and Power‑intent requirements.

Seniority Level

Mid‑Senior level

Employment Type

Contract

Job Function

Engineering and Information Technology

Industries

Software Development, Computers and Electronics Manufacturing, and Computer Hardware Manufacturing

#J-18808-Ljbffr