Title : Physical Design Engineer
Location : 100% Remote
Duration : Long Term Contract role
Responsibilities
- Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes.
- Resolve design and flow issues related to physical design, identify potential solutions, and drive execution
- Deliver physical design of an end-to-end IP or integration of ASIC / SoC design
Minimum Qualifications :
Bachelor's degree in Electrical Engineering, with 5 years of relevant physical design experienceStrong understanding in the RTL2GDSII flow and design tapeouts in 16nm / 14nm or below process technologiesExperience with low power implementation, power gating, multiple voltage rails, strong UPF / CPF knowledge.Experience working with most EDA tools like DC / Genus, ICC2 / Innovus, Primetime, Redhawk / Voltus, Calibre.Preferred Qualification :
Experience in running physical-aware logic synthesis and achieving optimal synthesis QoR on low power designsKnowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners / voltage definitions.Experience in Block-level and Full-chip floor-planning, power grid planningExperience with custom or regular clock tree synthesis implementation at block level or top level, and clock power reduction techniques.Experience with Python, TCL, Perl programming.#J-18808-Ljbffr