Senior Physical Design Engineer

As a Senior Physical Design Engineer, you will be responsible for the physical implementation of complex ASIC and interposer designs, from floorplanning to tapeout. You will work in a highly collaborative environment, leveraging Cadence design tools and Git for version control, ensuring efficient and high-quality execution. The ideal candidate is a self-starter who thrives with minimal supervision and has a strong background in advanced node physical design methodologies.

Responsibilities

• Drive full-chip physical implementation of 2.5D interposer and ASIC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization.
• Ensure design compliance with timing, power, and area (PPA) requirements , as well as DFM, DRC, and LVS constraints.
• Utilize Cadence tools (Innovus, Virtuoso, Tempus, Voltus, Pegasus, etc.) for physical design, verification, and signoff.
• Develop and execute timing closure strategies , working with STA engineers to meet performance goals.
• Optimize power distribution networks (PDN) and electromigration (EM) reliability in multi-die packaging environments.
• Work with package and system engineers to optimize die-to-die interconnect, bump placement, and TSV integration.
• Collaborate with RTL designers, DFT engineers, and backend teams to ensure seamless integration.
• Implement ECOs (Engineering Change Orders) and efficiently iterate design revisions.
• Utilize Git-based version control workflows for design database management and collaborative development.
• Identify and resolve congestion, signal integrity (SI), and crosstalk issues in complex designs.
• Ensure successful tapeout by running full-chip physical verification and working with foundry partners.

Qualifications

Required :

Preferred :

Skills

Required :

Preferred :

Job Location

More Information

For company description, benefits package, and application instructions see the Careers Page .

Phone : +1 331-701-7070

Fax : +1 331-701-7055

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