Silicon Power Analysis and Optimization Engineer - San Jose, CA - AMDJP00004575

Position Title : Power Optimization Engineer

Location : San Jose, CA (Hybrid)

Clearance Requirements : None

Position Status : Contract (W2 only)

Pay Rate : $90-$130 / hr

Position Description :

We are seeking a Power Optimization Engineer to support advanced low-power ASIC development. In this role, you'll drive RTL-level power optimization initiatives across IP design teams, working with state-of-the-art tools and methodologies to deliver energy-efficient silicon.

This hybrid position is based in San Jose, CA and offers the opportunity to collaborate with top engineering talent on high-impact projects in next-generation chip design.

Key Responsibilities :

• Develop and implement IP-level RTL power optimization methodologies in alignment with internal workflows.
• Automate power data collection and track key power metrics throughout development.
• Perform RTL and gate-level power roll-up and analysis.
• Partner closely with RTL and physical design teams to identify and implement power-saving opportunities.
• Ensure accuracy and consistency using industry-standard power analysis tools.

Required Skills & Experience :

About Seneca Resources

At Seneca Resources, we are more than just a staffing and consulting firm-we're a trusted career partner. With offices across the U.S. and clients ranging from Fortune 500 companies to government agencies, we connect top talent with meaningful opportunities.

When you work with Seneca, you're choosing a company that invests in your success. Our contractors enjoy :

We proudly foster an inclusive workplace and are an Equal Opportunity Employer . All qualified individuals, regardless of background, are encouraged to apply.