Hybrid / / Physical Design Engineer-ASICs, SoCs, VLSI

Hybrid / / Physical Design Engineer-ASICs, SoCs, VLSI

Physical Design Engineer-ASICs, SoCs, VLSI

Full time

Sunnyvale, CA

Job Description :

Key Responsibilities :

Block-Level Physical Design :

• Floorplanning & Partitioning – Define optimal floorplan with power grid, macro placements, and congestion analysis.
• Strong scripting experience.
• Placement & Optimization – Perform standard cell placement, legalization, and optimization to improve area, power, and timing.
• Clock Tree Synthesis (CTS) – Design and optimize low-skew, high-performance clock networks .
• Routing & DRC Closure – Ensure successful global and detailed routing , meeting design rule constraints.
• Timing Closure – Work on setup / hold timing violations , signal integrity, and cross-talk reduction using static timing analysis (STA) .
• Power & IR Drop Analysis – Optimize power planning, power integrity (IR drop, EM), and leakage reduction techniques .

Top-Level Physical Design :

Seniority level

Mid-Senior level

Employment type

Full-time

Job function

Information Technology

Industries

IT Services and IT Consulting

#J-18808-Ljbffr