Description
- Define logic architecture of various blocks of the design
- Design these blocks using Verilog and verify their block level functionality through simulation
- Document the design and review with the rest of the team
- Drive FPGA tools to compile the code and ensure timing closure
- Verify proper operation of your circuit via system level test with test hardware
- Work with the verification engineer to validate your circuit in a whole chip simulation environment
- Work with customer support to reproduce and fix issues found in the field
- Reproduce customer environment to reproduce any failures found in the field
- Fix the RTL, recompile the FPGA and review the changes with the team
Requirements :
- BS in EE, CS or Computer Engineering required
- MS in EE is a plus
- Experience with one or more of the following protocols : PCIe, CXL, NVMe, USB, SAS, SATA
- Experience with Monitoring and / or Test & Measurement tools
- Knowledge in AMD-Xilix Vivado and RTL simulation
- Strong interpersonal, organizational and communication skills
- Experience at working both independently and in a team-oriented, collaborative environment is essential
Salary Range :
$139,700.00-$187,770.000
Pay Transparency
The anticipated salary range listed for this role is only an estimate. Actual compensation for successful candidates is carefully determined based on several factors including, but not limited to, location, education / training, work experience, key skills, and type of position.
Teledyne and all of our employees are committed to conducting business with the highest ethical standards. We require all employees to comply with all applicable laws, regulations, rules and regulatory orders.
Our reputation for honesty, integrity and high ethics is as important to us as our reputation for making innovative sensing solutions.
Teledyne is an Equal Opportunity / Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability or veteran status, age, or any other characteristic or non-merit based factor made unlawful by federal, state, or local laws.
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