FPGA Design Engineer
A client of Innova Solutions is immediately hiring a FPGA Design Engineer. Position Type : Full time Contract Duration : 06-12 Months Location : Reston, VA 20191 (Onsite) As a FPGA Design Engineer, you will :
- Experience mapping algorithms and standards (Ethernet, TCP / IP, AXI) to hardware and architecture / system design tradeoffs.
- Proficient in VHDL design process and FPGA flow.
- Knowledge of Ethernet, TCP / IP protocols.
- Strong logic / board debug, and analytical skills.
- Excellent written, verbal, and presentation skills.
- Derive engineering specifications from system requirements and develop detailed architecture.
- Execute design (RTL AND / OR HLS (C++ to RTL)) and RTL quality (RDC, CDC, Formal, Lint).
- Generate test plans.
- Perform module level verification, synthesis / STA, Lab debug, SW driven validation on Linux based SOC evaluation boards
- Silicon / FPGA bring up, characterization and production ramp / support / collateral.
- High Level Synthesis (HLS) with Vivado, Embedded SW C++ (OOP) and System Verilog Assertions (SVA).
- Knowledge of high-speed protocols (PCIe, TCP / IP, Ethernet).
- VHDL Experience is required for all candidates to be considered.
- Proficient in VHDL >
5 yrs, Xilinx FPGA design EDA- Vivado.
Must have done hands on multiple complex designs arch / design / verification / Synthesis / STA.Working with Ethernet protocol (not just instantiating the IP) Is a big plus.Mentor EDA CDC / Lint / AC / RDC.The ideal candidate will have :Bachelor's degree in electrical engineering or equivalent degree, and minimum 4 years of prior relevant experience or Master's Degree plus 2 years of prior relevant experience developing, implementing, and verification of high-performance communications / networking ASIC / FPGA products.Prior experience in Aerospace / DefenseExperience in C++ (OOP).Experience in Xilinx MPSOC design with writing / debugging with SDKs, BSPs on bare metal / PetaLinux OS.Experience with High level synthesis (Xilinx Vivado HLS, AND / OR Mentor Calypto).Experience with Universal Verification Mythology (UVM).Experience with project leadership and EVM.