Design Verification Engineer

Title : Design Verification Engineer

Location : San Jose, C

s a Design Verification Engineer, you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems.

Responsibilities

• Triage regression failures and make testbench updates
• Debug functional errors in RTL model using simulation and debug tools.
• Maintain efficient and clean regression status
• Develop Scalable SystemVerilog / UVM testbenches for unit level and / or Cluster level verification.
• Review Architecture and Micro-Architecture specifications.
• Closely work with Architects and RTL designers.
• Define, maintain, and execute unit level and / or Cluster level verification testplans.
• Generate and run Testcases on logic simulation models.
• Code Functional coverage models and System Verilog assertions.
• Drive Functional Coverage and Code coverage to closure.
• Integrate C++ reference model into Scoreboards

Requirements