Design Verification EngineerBayone • San Jose, CA, United States
Design Verification Engineer
Bayone • San Jose, CA, United States
2 days ago
Job type
- Full-time
Job descriptionCandidate local to the San Jose market. (Top 2 candidates only per supplier only) Current state-of-the-art testbench development such as UVM methodology Experience in design verification with UVM and SystemVerilog is a MUST Triage regression failures and make testbench updates Debug functional errors in RTL model using simulation and debug tools. Maintain efficient and clean regression status Develop Scalable SystemVerilog / UVM testbenches for unit level and / or Cluster level verification. Review Architecture and Micro-Architecture specifications. Closely work with Architects and RTL designers. Define, maintain and execute unit level and / or Cluster level verification testplans. Generate and run Testcases on logic simulation models. Code Functional coverage models and System Verilog assertions. Drive Functional Coverage and Code coverage to closure. Integrate C++ reference model into Scoreboards 5-15 year's industry experience in a design verification role. Proficient in System Verilog / UVM / OVM, OOP / C++ Knowledge of GPU, experience with Shader, Texture, or Memory System a plus Experience with code coverage and functional coverage driven verification methodology. Experience in creating, running and debugging of SystemVerilog / UVM constraint-random Testbench. Excellent working knowledge of scripting languages such as Python or Perl. Understanding of micro-architecture, logic design, FSMs, arithmetic datapath pipelines. Strong functional verification experience including Test planning, Testbench Architecture, Test / Coverage Model / Assertion Development. Strong debugging skills Strong programming skills with good understanding of algorithms and data structures Good verbal and written communication skills.
We have 1 opening in Austin and another opening in either San Jose or San Diego.
- Hybrid 3 to 4 day per week
Reminder
NO H1B or anyone that will need a H1B Sponsorship
Open to 1099 or C2C, but candidate must be a direct 1 : 1 with your firm.
Technical Description :
As a Design Verification Engineer you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems. Responsibilities
Requirements
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Design Verification Engineer • San Jose, CA, United States
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