Company : Qualcomm Technologies, Inc.
Job Area : Engineering Group >
ASICS Engineering
General Summary : Join Qualcomm's design verification team in verifying the high‑speed mixed‑signal IP designs (PCIe, USB, MIPI, CXL, C2C, D2D, DDR, PLL, DAC, ADC, Sensors, etc.) for exciting products targeted for 5G, AI / ML, compute, IOT, and automotive applications. The team is responsible for the complete design verification lifecycle, from system‑level concept to tape out and post‑silicon support.
Responsibilities
- Define pre‑silicon and post‑silicon test‑plans based on design specs and using applicable standards working closely with design team.
- Architect and develop the testbench using advanced verification methodology such as SystemVerilog / UVM, analog / mixed‑signal simulation, low‑power verification, formal verification and gate‑level simulation to ensure high design quality.
- Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure.
- Work with digital design, analog circuit design, modeling, controller / subsystem and SoC integration teams to complete the successful PHY level verification, integration into subsystem and SoC, and post‑silicon validation.
- From scratch VIP development experience for Serdes controller + PHY is an additional plus.
Required For This Role
Master’s / Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.2+ years ASIC design verification, or related work experience.Knowledge of a HVL methodology like SystemVerilog / UVM.Experience working with various ASIC simulation / formal tools such as VCS, Xcellium / NCsim, Modelsim / Questa, VCFormal, Jaspergold, 0In and others.Preferred Qualifications
Experience with low‑power design verification, formal verification and gate‑level simulation.Knowledge of standard protocols such as PCIe, USB, MIPI, LPDDR, etc.Experience in scripting languages (Python, or Perl).Experience with mixed‑signal IP design verification, such as USB, PCIe, CXL, C2C, D2D, MIPI, UFS, DDR, PLL, data converters (DAC, ADC), or sensors.Minimum Qualifications
Bachelor’s degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.Master’s degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.Pay Range And Other Compensation & Benefits : $140,000.00 - $210,000.00. This pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location. Salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants. Our highly competitive benefits package supports your success at work, at home, and at play.
Equal Opportunity Employer : Qualcomm is an equal opportunity employer. Applicants with a disability may request accommodations during the application / hiring process; contact disability‑accommodations@qualcomm.com.
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