Design Verification Engineer : Mixed-Signal IP & SoC

A leading technology firm based in San Diego seeks an experienced ASIC Design Verification Engineer to verify high-speed mixed-signal IP designs. The ideal candidate has a degree in Electrical Engineering and at least 2 years of relevant experience. Responsibilities include defining testplans and developing testbenches using SystemVerilog / UVM methodologies. Competitive salary range of $140,000 - $210,000 with comprehensive benefits including bonuses and RSU grants.

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