Digital Design Engineer

Must Have skills :

FPGA design experience using Verilog, SystemVerilog, AMD / Xilinx FPGA design (Kintex / Virtex UltraScale+ desired, 7-series minimum)

RTL coding, synthesis and / or SoC Integration

Comms, working with other engineers, being proactive

Supplemental Skills, Plusses :

Experience using High Speed interfaces like PCIe, USB, MIPI

Experience in DFT / Testability requirement and test program definition

What are the top non-negotiable skill sets required for this role?

• Experience in RTL coding, synthesis and / or SoC Integration
• Experience in digital design µArchitecture
• Familiarity with Verilog, system Verilog coding
• Develop and test RTL modules on AMD / Xilinx FPGAs
• Develop and maintain build / simulation scripts using Python

Duties :

• Contribute to the development of efficient µArchitectures and contribute to ASIC digital µArchitecture, design and verification
• IPs integration
• Understand Design for Verification concepts
• Drive the top-level µArchitecture definition and develop the necessary RTL
• Drive the chip-level integration, verification plan development and verification
• Supervise the RTL-to-GDS flow and assist with synthesis and timing closure
• Support the test program development, chip validation and chip life until production maturity
• Work with FPGA engineers to perform early prototyping
• Support hand-off and integration of blocks into larger SOC environments
• Assist with Algorithm analysis, verification and improvement
• Contribute to ASIC digital architecture, design and verification

Skills

Must Have :

• 5+ years of FPGA design experience using Verilog, SystemVerilog
• 5+ years of experience in AMD / Xilinx FPGA design (Kintex / Virtex UltraScale+ desired, 7-series minimum)
• 4+ years of experience as a Digital Design Engineer and / or a Chip Lead
• Experience in RTL coding, synthesis and / or SoC Integration
• Experience in digital design µArchitecture
• BS Electrical Engineering / Computer Science or equivalent experience
• Experience with UPF based simulation flow
• System Verilog OVM / UVM experience
• Tcl and Python (or similar) scripting experience
• Experience in SoC integration and ASIC architecture

Wish List / Nice to Have :

• Experience in DFT / Testability requirement and test program definition
• Experience using High Speed interfaces like PCIe, USB, MIPI
• FPGA design
• Tensilica DSP, TIE, CNN, fixed point, floating point, python.
• Experience with Power Aware GLS flow
• MSEE / CS or equivalent experience

Education

• Must Have : Bachelor degree in Electrical / Computer Engineering or Computer Science
• Master's Degree preferred but not required
23 days ago