SOC Design Verification - Full-time

Job Description

Job Description

Positions are open for full-time SOC verification engineers from unit level to chip level as well as all aspects of verification such as functional, microarchitecture, and formal in particular in the areas of DDR memory, Ethernet, PCIe, and Fabric. We are looking for all levels of talent, from entrance to advanced level of experience.

Responsibilities

• Work closely with architecture and RTL designers on verifying the functionality correctness of the design
• Reviewing Architecture and Design Specifications
• Develop test plans and test environments
• Develop tests in assembly, C / C++, SystemVerilog, or vectors according to test plans
• Develop coverage monitors and analyze coverage to ensure all the test cases in the plans are covered
• Develop checkers in SystemVerilog or C-base transactors to verify the design
• Write assertions and apply formal verification to the designImplementing test benches, generating directed / constrained random tests
• Debugging failures, running simulations, tracking bugs
• Handling schedules and supporting multi-functional engineering effortAssisting in verification flows, automation scripts and regressions

Requirements

Education and Experience

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.