PIC Design Engineer

About Celestial AI

As Generative AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOCs) to systems of chips. In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the system's interconnect bandwidth, memory bandwidth, and memory capacity. Celestial AI's Photonic Fabric™ is the next-generation interconnect technology that delivers a tenfold increase in performance and energy efficiency compared to competing solutions.

The Photonic Fabric™ is available to our customers in multiple technology offerings, including optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB). This allows customers to easily incorporate high bandwidth, low power, and low latency optical interfaces into their AI accelerators and GPUs. The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging processes. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies.

This innovation empowers hyperscalers to enhance the efficiency and cost-effectiveness of AI processing by optimizing the XPUs required for training and inference, while significantly reducing the TCO2 impact. To bolster customer collaborations, Celestial AI is developing a Photonic Fabric ecosystem consisting of tier-1 partnerships that include custom silicon / ASIC design, system integrators, HBM memory, assembly, and packaging suppliers.

ABOUT THE ROLE

In this role, you will be a key part of the team responsible for the design and layout of very large-scale Silicon Photonic ICs (PICs) that interface directly with co-designed ASICs from advanced technology nodes at TSMC.

ESSENTIAL DUTIES AND RESPONSIBILITIES

• Contribute to the design and layout of very large-scale Silicon Photonic ICs (PICs) that interface directly with co-designed ASICs.
• Contribute to PIC delivery, all the way from floor-planning and top-level block placement to micro-architecture, optical & electrical routing, and back-end DRC and LVS verification.
• Work in conjunction with broader analog, digital and packaging teams to drive PIC physical design in accordance with product requirements related to opto-electronic performance, signal integrity (SI) & power integrity (PI).
• Work closely with the rest of the Photonics team to optimize layout flows and add to existing software base for automated design and verification.

QUALIFICATIONS

LOCATION : Santa Clara, CA

For California Location :

As an early stage start up, we offer an extremely attractive total compensation package inclusive of competitive base salary, bonus and a generous grant of our valuable early-stage equity. The target base salary for this role is approximately $185,000.00 - $225,000.00. The base salary offered may be slightly higher or lower than the target base salary, based on the final scope as determined by the depth of the experience and skills demonstrated by candidate in the interviews.

We offer great benefits (health, vision, dental and life insurance), collaborative and continuous learning work environment, where you will get a chance to work with smart and dedicated people engaged in developing the next generation architecture for high performance computing.

Celestial AI Inc. is proud to be an equal opportunity workplace and is an affirmative action employer.

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