Principal Digital ASICS designer

Job Type

Direct Hire - Full-time

Applicants must be legally authorized to work in the United States.

Compensation

$90,000 - $130,000 per year

Work Location

Hybrid 3 days onsite, 2 days remote.

Location in Valencia (Santa Clarita), CA.

Benefits

Medical insurance

Vision insurance

Dental insurance

401(k)

Pension plan

Paid maternity leave

Paid paternity leave

Work Schedule

Mon-Fri 8 AM to 5PM PST

Hybrid 3 days onsite, 2 days remote

Travel

Less than 10%.

Relocation

Paid lump sum upon relocation.

Company Description

Evinex is a staffing firm focused on connecting the right people with the right businesses. This is a permanent direct hire position for one of our prestigious Information Technology & Medical clients.

Job Description

Evinex is thrilled to partner with our client in their search for a Principal Digital ASICs Engineer, a role that sits at the forefront of innovation in hearing system technologies.

This position calls for an exceptional individual with a proven track record in digital ASIC design, ready to take on the challenge of developing cutting-edge solutions within the medical device sector.

The ideal candidate will not only bring a wealth of experience in ASIC design and development but also exhibit a deep understanding of data governance and the ability to adapt to rapid technological advances.

As a key member of the team, you will lead efforts to design, verify, and implement complex ASICs that push the boundaries of current medical technology.

Your work will involve close collaboration with cross-functional teams to create microarchitecture plans, develop and modify digital IPs, and ensure the scalability, reliability, and security of our systems.

In addition to your core responsibilities, your expertise in low-power design techniques, mixed-signal ASIC design, and advanced simulation tools will be instrumental in driving our projects to successful completion.

This role is not just a job; it's an opportunity to make a significant impact in the lives of those with hearing impairments.

Based in Valencia (Santa Clarita), CA, with a hybrid work model, the client offers competitive compensation, comprehensive benefits, and the chance for professional growth in a dynamic and supportive environment.

If you are a visionary engineer passionate about leveraging technology to improve quality of life and eager to take on new challenges in a company with a strong entrepreneurial mindset, we invite you to join us in shaping the future of hearing system technologies.

Why Join

The client is leading the industry in innovative technologies and requires a mid-senior professional to design and modify electrical parts or other hardware systems and applications for hearing systems and hearing platforms.

Responsibilities and Duties

Participate in mixed-signal ASIC development activities with cross-functional teams including chip architecture, specification, design, verification, validation, fabrication, packaging, debugging, test development, failure analysis, and documentation.

Create new digital block level microarchitecture, plan work breakdown, and design digital logic blocks.

Modify existing in-house digital IPs to extend functionality and / or to be compatible with new tools and workflow for reuse.

Create block and IC level digital V&V test plan and develop test bench.

Perform RTL simulation & verification including pre-tapeout FPGA level emulation, and post-silicon debug & characterization.

Develop, improve, and maintain in house digital design workflows.

Collaborate with contract digital designers for in house designs.

Work with fabless IC design vendors in either the turn-key or co-development models.

Perform digital backend activities for small test chip development tapeout with inhouse tools, if needed.

Other duties as assigned

Knowledge / Skills / Abilities Required

Must have :

Microsoft Office (Excel, Word, PowerPoint, Visio)

VHDL, Verilog, or SV, Questa or equivalent design verification tool

Jira, GitHub, Confluence

Python, C / C++, Make, LINT, CDC, Synthesis, UVM, STA, ATPG, DFT

Nice to have :

High ability to document work, communicate effectively and clearly, and evaluate others engineering solutions.

Proficiency in advanced simulation and modeling tools like Cadence Spectre or Mentor Graphics.

Expertise in low-power design techniques and methodologies for power optimization.

Knowledge of mixed-signal ASIC design integrating analog and digital components.

Experience with System-on-Chip (SoC) design and development processes.

Familiarity with emerging semiconductor materials and processes, such as GaN or SiC.

Advanced skills in physical design and verification, including experience with tools like Synopsys IC Compiler or Cadence Innovus.

Proficiency in scripting languages for automation of design processes, such as TCL or Perl.

Knowledge of industry standards and protocols related to data communication and interfaces, such as PCIe or USB.

Experience with machine learning algorithms for optimization of digital signal processing tasks.

Certification in project management methodologies, such as PMP or Agile Scrum Master, to enhance project execution and team collaboration.

Education / Professional Experience

Must have :

At least 7 years of previous digital ASIC design.

Experience in design, and development of custom application digital peripherals, custom communication data link peripherals that connect to APB, AHB bus

Nice to have :

Master’s Degree in Electrical Engineering, Computer Science, or a related field

Experience with ASIC design in the medical device industry

Class 3 Medical Device experience including knowledge of relevant standards (IEC60601, EN45502, etc.)

Proficiency in advanced digital design techniques and methodologies

Publications or Patents in the field of digital ASIC design

Leadership experience or participation in cross-functional project teams

Certification in Advanced VLSI Design and Technology from a recognized institution

Additional Information

Applicants must be legally authorized to work in the United States.