FPGA Design/Verification Engineer
Description :
The selected candidate will be responsible for FPGA verification using the UVM methodology.
In this role, you will :
- Work with low SWaP, radiation hardened, space rated devices.
- Devise a unique verification plan for a given design.
- Use SystemVerilog and Universal Verification Methodology (UVM) to verify a design in a Linux-based high-performance computing environment.
- Develop requirements, test cases, build test benches, generate reports, and document verification results.
Must have Skills :
- Experience with UVM verification methodology
- Experience developing test cases based off given requirements.
- Experience building test benches for FPGA / ASIC designs to provide randomized stimulus.
- Experience identifying and implementing necessary test exclusions.
- Experience generating coverage reports (code and functional)
Hands on experience with UVM and closing functional and code coverage is required for this role.
If you are a military professional seeking impactful work in the civilian sector, consider exploring ICONMA’s job opportunities and contributing your expertise to the continued success of America’s Defense Industry.
We thank you for your service and expertise, we would like to offer our expertise as a service to you in your future career endeavors.
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