On-Site Just South of Minneapolis, MN starting in November
Ready to make your application Please do read through the description at least once before clicking on Apply.
2 Year+ Contract
Senior FPGA Design Engineer
SystemVerilog, Xilinx
Experience working in the Vivado tool
IP Integrator (Block Design)
Design Flow
Timing Constraints
IP Manager
Isolation Editor
Experience with Ethernet Frame structure & protocols.
Experience with QuestaSim or ModelSim
Experience with scripting languages (TCL, Bash, Make)
Fpga Design Engineer • Saint Paul, Minnesota, US