Senior HSIO Validation Engineer

NVIDIA’s invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing — with the GPU acting as the brain of computers, robots, and self-driving cars. Today, we are increasingly known as “the AI computing company.” We are actively looking to add the smartest brains to our company and usher in the next wave of computing.

NVIDIA’s Silicon Solutions Group is responsible for crafting NVIDIA’s GPUs and SoCs into groundbreaking platforms for autonomous machines, Cloud and Data Centers, Deep learning, High-Performance Computing, Gaming, and Entertainment solutions.

What you'll be doing :

Drive the planning and execution of NVLINK / C2C or similar interfaces in the areas of functional bring-up, system-level validation, productization and troubleshooting for NVIDIA GPUs and SOCs.

Drive schedule, programming guides, customer critical issues, manufacturing yield improvements, and design feedback. Investigate technically complicated HSIO bugs and help drive debug efforts across various teams

Coordinate with logic design, circuit design, board design, Simulation, diagnostics, ATE, firmware, driver, and marketing teams to drive the chip into production.

Develop new methodologies to improve the silicon validation process, which will help meet upcoming performance, adaptability, and safety industry standards.

Ensure interoperability with connected devices and system components in sophisticated interconnect topologies.

Engage proactively with multi-functional engineering teams, including system architects, mixed-signal design, DGX, software / firmware, hardware / software quality assurance, operations, and application engineering to facilitate the design, development, troubleshooting, and release of upcoming products.

What we need to see :

BS or MS in Electrical or Computer Engineering (or equivalent experience) and a minimum of 8 years of relevant experience

In depth understanding of PCIe (or similar) protocol and characterization / validation methods in post-silicon environment

Excellent knowledge of Signal integrity concepts, Silicon characteristics and high speed / SERDES functional validation

Good knowledge of lab equipment (DSOs, BERT, Protocol / Logic analyzers) and Hands-on Post-Si bring up, functional validation of HSIO interfaces

Understanding of firmware / driver structures and their interaction with HW.

Strong in scripting languages (Perl, Python) to write direct test / debug programs for stress and failure analysis

Strong project management, collaboration, and communication skills

NVIDIA is leading the way in groundbreaking developments in Artificial Intelligence, High-Performance Computing, and Visualization. Our invention, the GPU, serves as the visual cortex of modern computers and is at the heart of our products and services. Our work opens up new universes to explore, enables outstanding creativity and discovery, and powers what were once science fiction inventions, from artificial intelligence to autonomous cars. NVIDIA is looking for extraordinary people like you to help us accelerate the next wave of artificial intelligence.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.

You will also be eligible for equity and benefits () .

Applications for this job will be accepted at least until October 31, 2025.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.