ASIC Engineer, Formal Verification

Overview

Meta is hiring ASIC Formal Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Formal Verification to build IP and System On Chip (SoC) for data center applications. As a Formal Verification Engineer, you will be part of a team working with the best in the industry, focused on developing innovative ASIC solutions for Meta's data center applications. You will be developing comprehensive formal testplans and be responsible for complete formal verification sign-off of single or multiple complex blocks. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.

Responsibilities

Provide technical leadership in Formal Verification

Propose, implement and evangelize the Formal Verification Methodology to be used across the group, both at the top level and at the block level

Work with Architecture and Design team to come up with formal specification and implementation

Define formal verification scope, create formal environment and close coverage with targeted Formal Verification Techniques at IP, Subsystem and SoC level

Build reusable / scalable environments for Formal Verification and deploying the tools

Evaluate and recommend EDA solutions for Formal Verification

Provide training for internal teams and mentoring engineers related to Formal Verification Technology

Minimum Qualifications

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience

8+ years of experience in Design Verification

5+ years of experience in Formal Verification

Experience with Formal Verification applications including Datapath, sequential equivalence, Xprop, Clock Gating, connectivity etc

Proven understanding of Formal Verification methodologies, complexity reduction techniques and abstraction techniques

Proven analytical skills to craft novel solutions to tackle industry-level complex designs

Demonstrated experience with effective collaboration with cross functional teams

Fluency in hardware description languages, such as SystemVerilog and SVA

Proficiency in scripting languages such as Python, Perl, or Tcl

Experience with JasperGold or VC-Formal

Preferred Qualifications

Experience to quickly understand and interpret specifications and extract design behaviors / properties

Experience in formal property verification of complex compute blocks such as DSP, CPU, GPU or HW accelerators

Experience with complex SoCs

Formal verification experience in clock domain crossing, IP-XACT based register verification and low power

Experience with development of fully automated flows from specification to fully verified designs

Experience with simulators and waveform debugging tools

Public Compensation

$173,000 / year to $249,000 / year + bonus + equity + benefits

Industry

Internet

Equal Opportunity

Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.

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