System IP Design Verification Engineer

Job Title : System IP Design Verification Engineer

Duration : 6+ Months

Location : Onsite at Austin, TX, USA OR San Jose, CA,

Description :

We are currently looking for exceptional hardware verification engineers to join our System IP team in our Austin, TX R & D Center in San Jose, CA. System IP team develops proprietary coherent interconnect and memory controller IPs deployed in many high-volume products.

Job Description :

As a Senior Staff System IP Design Verification Contractor you will contribute to the functional verification of System IP including coherent interconnect and caches.

This is a technical individual contributor role with heavily involved hands-on project execution.

A strong background in Design Verification and hands-on experience with both block-level and top-level is required to be successful in this role.

Key responsibilities include :

• Architecting and building re-usable testbenches right from scratch
• Proposing and driving best practices / methodologies / automation that can improve productivity
• Owning key features and timely execution of tasks as per milestones
• Experience with GLS [gate level simulation]
• Creating test plans as per spec and presenting to various stakeholders
• Working with designers to resolve any spec issues
• Creating test benches, verification environments, stimulus, tests
• Collaborating with designers to verify the correctness of a design feature, and resolve fails
• Developing assertions, checkers, covergroups, Systemverilog constraints
• Debugging and root causing functional fails from regressions
• Analyzing code and functional coverage results, performing gap analysis
• Working with SoC team to debug functional fails during IP bringup and feature execution
• Collaborating with Physical design teams, running and debugging gate-level simulations
• Collaborating with Performance verification teams to help with co-sim TB bringup
• Bringup power-aware verification with UPF
• Helping with Silicon bringup and root causing fails

Requirements

Minimum requirements :