Talent.com
Physical Design Lead Custom Silicon Management

Physical Design Lead Custom Silicon Management

MediabistroCupertino, CA, United States
30+ days ago
Job type
  • Full-time
Job description

Physical Design Lead Custom Silicon Management

Cupertino, California, United States | Hardware

Description

You will have the opportunity to integrate and develop new insights, as well as collaborate with vendors to promote efficiency within the Silicon community. We value your technical understanding of physical design principles. Your responsibilities will include :

  • Auditing vendor PD flows and methodologies for gaps and setup issues.
  • Recommending improvements to optimize QoR for Apple chips.
  • Collaborating with internal teams like systems and program management to ensure vendor PD implementation aligns with design goals.
  • Working with specialists from packaging, process, and related areas to resolve project issues.
  • Conducting detailed design reviews to ensure schedule adherence and high-quality work.
  • Reviewing final PD, STA, SI, electrical analysis reports, and signing off for tapeout approval.
  • Providing post-tapeout support, including ECOs and debugging.
  • Maintaining consistent operational standards across vendors and projects.
  • Fostering professional relationships with vendors while maintaining appropriate boundaries.

Minimum Qualifications

  • BS degree with 10+ years in Physical Design.
  • Knowledge of digital design concepts.

    • Preferred Qualifications

  • Experience leading physical design teams.
  • Proven track record of taping out complex chips from gates to GDS.
  • Knowledge of front-end design methodology, including RTL coding, synthesis, timing constraints, clock domain handling, and low power techniques.
  • Hands-on experience with P&R methodology : IO planning, ESD, floor planning, power planning, clock tree synthesis, timing closure, routing, DFM, and physical verification.
  • Proficiency with industry CAD tools such as Cadence, Synopsys, Mentor, or Atoptech.
  • Expertise in Static Timing Analysis, timing closure, and noise mitigation.
  • Experience in Power and Signal Integrity analysis.
  • Ability to debug LVS, DRC, Antenna, ERC issues.
  • Familiarity with analog layout practices for sensitive circuits.
  • Experience with mixed-signal SoC tapeouts involving multiple analog IPs.
  • Knowledge of low power / leakage management techniques.
  • Experience with IP extraction and characterization.

    • At Apple, compensation includes base pay within a range, with opportunities for growth based on skills, qualifications, and experience. The base pay range for this role is $172,100 to $305,600. Employees may also participate in stock programs, receive benefits such as medical coverage, retirement plans, discounts, educational reimbursements, and potential bonuses or relocation assistance.

    Note : Benefits, compensation, and stock programs are subject to eligibility and plan terms.

    Apple is an equal opportunity employer committed to diversity and inclusion, seeking to promote equal opportunity regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other protected characteristics. Learn more about your EEO rights as an applicant.

    #J-18808-Ljbffr

    Create a job alert for this search

    Design Lead • Cupertino, CA, United States