CPU Design Timing Engineer

Role Number : 200598926-0505

Summary

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In this role, you will be responsible for all aspects of timing including working with the implementation and RTL teams on timing changes, helping with construction / modify timing flows, timing analysis, and timing closure.

Description

As the CPU Design Timing Engineer, you will be responsible for the timing closure of the project.

Responsibilities include but are not limited to :

• Working with the CAD team to develop the timing flow that will be used on the project including scripting to improve analysis flows and engineer efficiency.
• Work extensively with CPU micro-architects and Implementation engineers to drive timing closure for the CPU.

Minimum Qualifications

Minimum BS and 10+ years of relevant experience

Experience with timing analysis

Experience with a static timing analysis tool such as PrimeTime® or Tempus®

Experience with TCL and either Perl or Python

Preferred Qualifications

Prior experience performing timing analysis in high speed digital designs such as CPUs or other similar designs

Understanding of physical design tools and methodology including logic synthesis, PnR, parasitic extraction, logic equivalence

Understanding of deep sub-micron technologies and scaling trends

Working knowledge of CPU microarchitecture including common fundamental timing paths

Working knowledge of clock-domain crossing and reset-domain crossing

Experience with with multiple clock and power domains

Experience with SDC command usage including clock definitions, timing exceptions, and IO constraints

Experience with noise analysis and fixing noise in designs

Experience with variation modeling in static timing analysis tools

Experience with RTL modeling and assertion based verification

Experience with data parsing, analysis, and representation / plotting

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