Silicon Architect, Reality Labs

Silicon Architect, Reality Labs

Reality Labs (RL) focuses on delivering Meta's vision through AI-first devices that leverage Mixed Reality (MR) and Augmented Reality (AR). The compute performance and power efficiency requirements of Mixed and Augmented Reality require custom silicon. The Reality Labs Silicon team is driving the state-of-the-art forward with highly integrated SoCs that leverage breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR & MR devices that blend our real and virtual worlds throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms. We are looking for a Silicon Architect who will collaborate with a world-class group of SoC and IP architects, modeling, development, and validation teams, firmware developers, and program managers to accelerate the development and market introduction of low power highly customized SoCs.

Responsibilities

Architecture definition and specification for improvements to the SoC chassis architecture

Specification for feature improvements to our chassis generators

Work cross-functionally with SoC and IP architecture, performance / power modeling, logic design and verification, physical implementation, firmware, CAD, and prototyping teams

Work effectively as an individual and in a multidisciplinary multi-site team

Minimum Qualifications

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience

5+ years of experience integrating SoCs or complex IP-based subsystems as a Silicon Architect or Digital Design Engineer

Experience in evaluating trade-offs such as speed, performance, power, area

Experience in employing scientific methods to debug, diagnose and drive the resolution of cross-disciplinary design issues

Hands-on experience in digital design, logic simulation, and performance analysis

Preferred Qualifications

Experience architecting or designing chip pervasive logic such as clock generation, reset, and power management of SoCs with multiple clock and voltage domains for battery-operated systems

Experience deploying chip pervasive logic such as clock generation, reset, and power management of SoCs with multiple clock and voltage domains for battery-operated systems

Experience deploying Networks-on-Chip (NoCs) leveraging on-chip interface protocols such as AMBA AXI for heterogeneous SoCs targeting consumer or mobile devices

Experience with developing tools to generate RTL

Experience with scripting languages like Python to facilitate task automation

Experience collaborating in a multi-site team environment