About Etched
Etched is building the world's first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
As a Substrate IC Package Layout Design Engineer , you will be responsible for the end-to-end design of complex IC substrate packages, supporting high-power consumption and high-speed signaling. The ideal candidate will have extensive experience with large substrate designs (>
50mm), complex power delivery networks, and high-speed signaling solutions (up to and beyond 50GHz). You will work closely with silicon, signal integrity, power integrity, and system help co-design world class substates with OSAT providers. Intense focus on optimization for power delivery through substrate, pushing what's possible.
Key responsibilities
Lead the design and development of complex IC substrate layouts for high-power AI processors and accelerators.
50mm) and complex multi-layer substrate packages with high pin counts and dense routing requirements.
700W custom silicon solutions.
Develop high-speed signal routing solutions capable of supporting >
50GHz signaling while minimizing signal integrity issues such as loss and crosstalk.
Optimize CoWoS (Chip-on-Wafer-on-Substrate) interposer designs for thermal and electrical performance.
Perform DRC (Design Rule Check) and LVS (Layout vs. Schematic) verification for all substrate designs.
You may be a good fit if you have
50mm) and complex high-density layouts.
50GHz) and mitigating signal integrity challenges (crosstalk, reflections, impedance mismatches).
Benefits
Compensation Range
How we're different
Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.
We are a fully in-person team in West San Jose, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.
Design Engineer • San Jose, CA, United States