Senior Design Verification Engineer

Hello.

Job Title : Design Verification Engineer

Location : San Jose, CA (Onsite)

Mode : Full Time (USC)

JD :

• 12+ years of experience in Design Verification expertise in System Verilog / UVM Unit / Module level Verification.
• Experience in test planning and debugging complex designs.
• Full silicon design lifecycle experience.
• Strong background in developing UVM Testbenches from scratch.
• Deep understanding of Computer Architecture.
• Test Planning, Coverage, Bring up Phase, Design Freeze and ECO Phase.
• Experience with caches and memory subsystems (preferred).
• C++ Nice to have

Thanks & Regards,

Sreelakshmi – Resource Specialist

Yochana IT Solutions Inc.

E : sreelakshmi@yochana.com

P : +1 248 833 6604

A : 23000 Commerce Drive, Farmington Hills, MI 48335

www.yochana.com