Our client is a global infrastructure technology leader built on more than 60 years of innovation within the semiconndutor and Manufacturing space for communications.
They are urgently seeking multiple engineers from
- Jr. PhD graduates with Solid therotical & relevant DSP experience
- Mid-level MS degrees with 5+ years in DSP and commubication algorithm development knowledge and experience and Ethernet PHY design
- Sr. level Digital Signal Processing (DSP) R&D Engineer with Ethernet and WIRELINE to join their growing team.
Responsibilities include :
Develop specification, architecture, and micro-architecture of digital signal processing and communications algorithmsBit-exact MATLAB / Simulink and C / C++ system modeling and simulationDevelop and run system level simulation suites of the copper Ethernet PHY transceivers and perform vector matching verification with RTL simulationsDefine and document chip requirements, architecture, verification and lab test planLab testing and debug of ASICsDocumentation / application note development and customer supportRequirements :
BS Degree in Electrical engineering is a MUST . with 10+ years experience, Master's in Elecetrical Engineering and 3+ years of related experience; or PhD in Digital Signal Processing is a MUSTKnowledge in Communication Theory & Digital Signal Processing algorithmsExperience in equalizers, Timing Recovery, Echo Cancellation and Gain Control algorithmsNice to Have Skills :
Experience in Wireline Algorithms -Experience in Ethernet 802.3 PHY TransceiversExperience in C / C++, MATLAB / Simulink,Experience architecting communications systems for high performance ASIC based products is highly desirableGood hands-on skills in the labGood oral and written communication skillsThe Offer :
140-180Kfull medical, dental, Vision401KPTOBonus potentialMotion Recruitment Partners
Posted by : Kevin Gabrielson
Specialization :
Network EngineeringEmbedded