RM - DFT Sr. Staff Engineer

Duration : 0-8 month(s)

Description / Comment : LEVEL 9

CM&T

Security Operations Center - DFT Engineer - Phoenix - DFT Security at Full SOC Level : Full Turn Key, ability to distill the requirements from the various block and chip lead, write the specification and write the RTL for all necessary wrapper and control logic Memory Bits : Foundry Compiler are used, SMS from Synopsis, Full Chip Memory Bist Test Chip : DFT full chip from JTAG to Bist to Mbist

What type of education is needed for this position? BS in Computer Science or Electrical Engineering

Work location : Phoenix, AZ

Will this role work remote / In Office / Hybrid (in office & remote) Remote is a possibility.

Does this role require vaccination mandate? Yes

Does the resource have to be Local : Preferred

Visa Restrictions (see red info below)? US Citizen or Green Card Holder

Will the client pay for travel and expenses? Yes, with prior approval

Is industry experience needed for this role and why? Yes, 3-7 years experience in semiconductor design and development.

must-have skills for this role?

1. Electrical Engineering

2. Electronic Design Automation (EDA)

3. Semiconductor Design & Development

Years of experience required for each skill? 3-7 years experience

nice-to-have skills :

1. Developing DFT specifications

2. Industry standard DFT and design tools

3. Debugging ATPG / MBIST patterns

What are the chances for extension? 100%, purely based on performance.

Please provide a robust job description : You Are :

An experienced DFT Engineer

The Work :

Work with the Silicon teams to document the DFT specifications and define the requirements

Develop and implement DFT architecture and infrastructure

Develop and drive execution of enhanced DFX (DFT / Design-For-Debug) methodologies, with increased focus on debug support

Work with the DV team to verify DFT implementations

Generate structural test vectors, analyze and improve coverage / test time / test cost

Work with designers on STA, physical, power and logical issues impacting DFT

Work with test engineers to bring up test vectors on silicon

Work with lab bring-up teams to bring up test vectors in the lab environment

Manage schedules and support internal and external cross-functional / cross-organizational engineering efforts

Here s what you need :

A minimum of three years of experience with Hardware Design-For-Test (DFT) engineering including

A minimum of three years of experience in uP and / or GPU and / or Video Processing

Bachelor s Degree or equivalent (12 years) work experience (If an, Associate s Degree with 6 years of work experience)

Bonus points if :

Developing DFT specifications

Industry standard DFT and design tools

Debugging ATPG / MBIST patterns

STA constraints and their interaction with DFT

Experience with Root Cause Analysis

IP / Top Scan insertion (all EDA solutions)

IP / Top Mbist insertion (all EDA solutions)

Scripting languages TCL / Perl / Python

Experience with Synopsys DFT tools (Tetramax, DFT compiler, BSD compiler, Formality, Spyglass)

Experience with JTAG and IEEE standards 1149.1 and 1149.6.

Additional Job Details : 1 - API Security (P3 - Advanced) 2 - Hardware Troubleshooting (P3 - Advanced)