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Asic design engineer • fort collins co
Senior Memory Design Engineer
Rival IncFort Collins, CO, United StatesThermal Design Engineer High Performance Workstation Computing
HPFort Collins, Colorado, USASenior Design Engineer - Water Treatment in Fort Collins
Energy Jobline ZRFort Collins, CO, United States2026 Undergrad ASIC Package Engineering Intern / Co-Op
AMDFort Collins, CO, USSilicon Design Analyst
Advanced Micro Devices, Inc.Fort Collins, CO, United States- Promoted
Package Design Engineer
Broadcom CorporationFort Collins, CO, United StatesEngineer Design
Church & DwightFort Collins, CO, USA- Promoted
Analog / Mixed-Signal IC Design Engineer
Omni Design TechnologiesFort Collins, CO, USMicroprocessor VLSI Physical Design Engineer
Advanced Micro Devices, IncFort Collins, Colorado, United StatesDesign Engineer
Colorado StaffingFort Collins, CO, United StatesDesign Engineer-Mechanical
Professional Engineering ConsultantFort Collins, CO, United States- Promoted
Design Engineer - Water Treatment
Mackay SpositoFort Collins, CO, USDesign Engineer
ActalentFort Collins, Colorado, USAPackage Design Engineer
Broadcom Inc.USA, Colorado, Fort Collins, 4380 Ziegler Road- Promoted
Transportation Design Engineer, Entry Level - CD0023
Felsburg Holt & UllevigFort Collins, CO, US- Promoted
Senior Memory Design Engineer
RivosFort Collins, CO, United States- Promoted
Design Engineer - Water Treatment
MacKay SpositoFort Collins, CO, United States- Promoted
Power Analysis Physical Design Engineer
TenstorrentFort Collins, CO, United States- Promoted
Senior Analog / Mixed-Signal IC Automation and Design Engineer. (copy)
Omni Design Technologies IncFort Collins, CO, United StatesThe average salary range is between $ 106,031 and $ 210,625 year , with the average salary hovering around $ 136,000 year .
- vp of engineering (from $ 150,625 to $ 249,738 year)
- vp engineering (from $ 153,950 to $ 226,600 year)
- technical program manager (from $ 104,380 to $ 221,400 year)
- technical director (from $ 121,869 to $ 215,000 year)
- software architect (from $ 136,716 to $ 213,750 year)
- solutions architect (from $ 135,000 to $ 213,750 year)
- engineering director (from $ 140,000 to $ 212,500 year)
- asic design engineer (from $ 106,031 to $ 210,625 year)
- cloud architect (from $ 133,900 to $ 210,000 year)
- data architect (from $ 125,000 to $ 207,750 year)
- Sacramento, CA (from $ 136,913 to $ 237,000 year)
- South Bend, IN (from $ 138,500 to $ 232,050 year)
- San Diego, CA (from $ 147,950 to $ 220,000 year)
- San Francisco, CA (from $ 147,500 to $ 220,000 year)
- San Mateo, CA (from $ 144,780 to $ 219,531 year)
- Santa Clara, CA (from $ 153,648 to $ 217,564 year)
- Sunnyvale, CA (from $ 152,250 to $ 217,500 year)
- San Jose, CA (from $ 145,486 to $ 215,000 year)
- Los Angeles, CA (from $ 140,000 to $ 214,180 year)
- El Cajon, CA (from $ 130,499 to $ 213,875 year)
The average salary range is between $ 128,729 and $ 200,607 year , with the average salary hovering around $ 161,272 year .
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Senior Memory Design Engineer
Rival IncFort Collins, CO, United States- Full-time
Rivos Custom Circuits team is seeking highly motivated candidates to develop state of the art custom SRAM memories, Register file memories, and compiled memories to improve circuit performance, optimize dynamic and static power and support silicon bring up. The role will be at the center of a state-of-the art circuit design effort, interfacing with all disciplines and have a critical impact on getting products to market quickly. The qualified candidate will be responsible for designing and delivering custom circuits from scratch. Candidates must have 8-10 years of experience in transistor level circuit design, circuit simulation, equivalence checking, PPA trade off analysis, low power design techniques, timing, noise and power characterization.
Key Qualifications
- The ideal candidate will have 12-15 years of custom circuit design experience from RTL-GDS for CPU and SoC applications
- Prior experience and proven success of successfully designing high performance SRAM memories, Register file memories, SRAM compilers, data path designs and standard cells
- Experience designing transistor-level custom circuits in advanced FinFET technology nodes
- Must have a solid experience with the custom circuit tool flows for delivering design collaterals
- A solid understanding of device physics, process technology and circuit design techniques for high performance, low power, and power gating
- Experience with advanced process design rules and supervising mask design
- Knowledge developing automation for compilers and standard cells
- Post-Silicon test and debug experience
- Ability to work well in a team and be productive under aggressive schedules.
- Excellent problem solving, written and verbal communication
Responsibilities
Education and Experience
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