Staff Design Verification Engineer (Memory Controller)
Samsung Electronics PerSan Jose, CA, United States2 days ago
Job type
- Full-time
Job descriptionPosition Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us! Role and Responsibilities As a System IP Design Verification Engineer you will contribute to the functional verification of LPDDR memory controllers. This is an individual contributor role, heavily involved in hands-on project execution. A strong background in Design Verification and hands-on experience with both block-level and top-level is required to be successful in this role. You architect and build re-usable testbenches right from scratch You propose and drive best practices / methodologies / automation that can improve productivity You own key features and timely execution of tasks as per milestones You create test plans as per spec and present to various stakeholders You work with designers to resolve any spec issues You collaborate with designers to verify the correctness of a design feature, and resolve fails You develop assertions, checkers, covergroups, Systemverilog constraints You analyze and debug, root causing functional fails from regressions You perform coverage gap analysis, identifying coverage exclusions and improving stimulus You integrate memory models (VIP) from vendors into TB and bringup You develop fake PHY models and bringup, and bringing up real PHY You verify DRAM interface training, Link ECC / EDC, Command / WR / RD paths, Schedulers, DVFS, Power Down, Self-Refresh You work with SoC team to debug functional fails during IP bringup and feature execution You collaborate with Performance Verification teams to help with co-sim TB bringup You help with Silicon bringup and root causing fails You mentor junior team members, work independently, and are a team player Skills and Qualifications 10+ years of experience with a Bachelors degree in Computer Science / Computer Engineering / relevant technical field, or 8+ years of experience with a Masters degree, or 6+ years of experience with a PhD 8+ years industry experience in a design verification role Expert hands-on coding skills in Testbench, Stimulus, checker development & coverage closure. Experience with System Verilog, UVM or equivalent Experience with LPDDR5 / 5X / 6 memory model VIPs Experience with DDR / LPDDR / HBM protocols Experience with Git version control, Unix / Perl / Python scripting Combined experience with coherent interconnect, caches, and LPDDR memory controllers is highly preferred Formal verification skills will be a plus Good written and verbal communication skills Our Team Our System IP team develops proprietary coherent interconnect and memory controller deployed in many high-volume products. Our team plays a key role in influencing the product roadmap for a market-leading system IP solutions. We focus on delivering system modeling capability based on optimization and use-case-driven analysis (gaming, computational photography) that enables a world-class memory subsystem.With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.Being part of a new team of talented individuals with vastly diverse backgrounds and skill sets at a well-established global company means you have limitless room to explore, innovate, and expand role responsibilities to build technical expertise. With a big charter ahead, we get to do challenging work and solve unique problems in a highly collaborative and supportive environment. You will always be learning while helping us shape the teams culture. Total Rewards At Samsung SARC / ACL, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $151,000 and $239,200. Your actual base pay will depend on variables that may include your education skills, qualifications, experience, and work location. This is an exempt position, which is not eligible for overtime pay under the Fair Labor Standards Act (FLSA).Samsung employees have access to benefits including : medical, dental, vision, life insurance, 401(k), free onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and many more. In addition, regular full-time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance.Additionally, this role might be eligible to participate in long term incentive plan and relocation. U.S. Export Control This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information. Trade Secrets By submitting an application, you [applicant] agree[s] not to disclose to Samsung, or induce Samsung to use, any confidential or proprietary information (including trade secrets) belonging to any current or previous employer or other person or entity.#SARC #ACL Please visit to see Privacy Policy, which defaults according to your location. You can change Country / Language at the bottom of the page. If you are European Economic Resident, please click . Samsung Electronics America, Inc. and its subsidiaries are committed to employing a diverse workforce, and provide Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.
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Design Verification Engineer • San Jose, CA, United States
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