Machine learning engineer • austin tx
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The average salary range is between $ 144,900 and $ 225,000 year , with the average salary hovering around $ 171,600 year .
The average salary range is between $ 124,693 and $ 200,000 year , with the average salary hovering around $ 154,997 year .
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Custom SoCs (System on Chip) are at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team, you'll be responsible for designing and optimizing hardware in our data centers, including AWS Inferentia and Trainium systems—our custom-designed machine learning inference and training servers. Our success depends on world-class server infrastructure as we handle massive scale and rapidly integrate emerging technologies. We're looking for an ASIC DFT Design Engineer to help us trailblaze new technologies and architectures while ensuring high design quality and making the right trade-offs.
Key job responsibilities
•Define and develop state-of-the-art Design for Test (DFT) architectures for advanced technology nodes
• Work closely with block designers and physical design (PD) team to implement highly efficient DFT solutions
• Perform RTL coding and Verification using Verilog/System Verilog
• Utilize industry standard DFT tools to create high coverage and cost-effective test patterns to target advanced silicon defects
• Participate in Silicon debug efforts alongside ATE and System teams
• Communicate and work with team members across multiple disciplines
BASIC QUALIFICATIONS
- Bachelor's degree in Electrical or Communications Engineering or a related field
- 5+ years of practical DFT experience with complex SoC designs in advanced technology nodes
- Experience with standard tools and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time
- Experience with automation script development
PREFERRED QUALIFICATIONS
- Master's degree in Electrical or Communications Engineering or a related field
- Practical experience developing STA constraints for DFT modes and working directly with PD teams to close timing
- Experience with RTL coding and design verification (DV) flows
- Experience with gate-level simulation setup and debug with SDF
- Strong programming and scripting skills in Perl, Python or Tcl
- Practical experience with silicon debug and yield optimization
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