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Verification engineer Jobs in Berkeley, CA
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Verification engineer • berkeley ca
- Promoted
Design Verification Engineer
Quix Recruitment Group LtdSan Francisco, CA, United States- Promoted
Senior Solutions Engineer — Lending Verification SaaS
Checkr, Inc.San Francisco, California, United StatesInsurance Verification Specialist
VirtualVocationsOakland, California, United States- Promoted
Design Verification Engineer
AppleSan Francisco, California, United States- Promoted
Design Verification Engineer
Apple Inc.San Francisco, California, United States- Promoted
System Verification & Validation (V&V) Engineer
CapgeminiSan Francisco, CA, United States- Promoted
Junior ASIC Verification Engineer - Impactful Design
Cisco SystemsSan Francisco, CA, United StatesAnalog / Mixed- Signal Verification Engineer
Sigma Connectivity Inc.Bay Area, CA, United States- Promoted
Systems Engineer, Platform Requirements and Verification
Waabi Innovation Inc.San Francisco, CA, United States- Promoted
Senior Solutions Engineer – Asset & Income Verification
CheckrSan Francisco, California, United States- Promoted
Verification Engineer
Eridu CorporationSan Francisco, CA, United States- Promoted
Design Verification Engineer
Amadeus SearchSan Francisco, CA, United States- Promoted
CPU Verification Engineer
AmazonSan Francisco, CA, United States- Promoted
Design Verification Engineer
EDA CAREERS, (Technology Futures Inc).San Francisco, California, United States- Promoted
ASIC Design Verification Engineer (all levels)
SQL Pager LLCSan Francisco, California, United StatesSenior Digital Verification Engineer
Ethan Alexander GroupSan Francisco, CA, US- Promoted
Design Verification Engineer
OpenAISan Francisco, CA, United States- Promoted
Design Verification Engineer
Eridu AISan Francisco, California, United States- Promoted
Sr Design Verification Engineer (DSP)
Encore Semi, Inc.San Francisco, California, United StatesThe average salary range is between $ 92,625 and $ 205,000 year , with the average salary hovering around $ 141,000 year .
- software development manager (from $ 220,000 to $ 273,000 year)
- nuclear medicine (from $ 153,470 to $ 250,984 year)
- veterinarian (from $ 115,000 to $ 250,000 year)
- python developer (from $ 135,000 to $ 244,125 year)
- office administrative assistant (from $ 47,840 to $ 243,900 year)
- vp of engineering (from $ 68,428 to $ 237,500 year)
- embedded systems engineer (from $ 133,875 to $ 222,134 year)
- product director (from $ 157,500 to $ 220,750 year)
- applications engineer (from $ 149,709 to $ 218,500 year)
- startup (from $ 136,250 to $ 216,250 year)
- Palm Bay, FL (from $ 153,813 to $ 224,450 year)
- Spokane Valley, WA (from $ 145,486 to $ 217,750 year)
- Berkeley, CA (from $ 92,625 to $ 205,000 year)
- Seattle, WA (from $ 112,500 to $ 201,928 year)
- San Diego, CA (from $ 138,612 to $ 200,428 year)
- Dallas, TX (from $ 73,840 to $ 196,750 year)
- Boston, MA (from $ 109,850 to $ 196,750 year)
- Los Angeles, CA (from $ 116,189 to $ 192,878 year)
- Washington, DC (from $ 110,778 to $ 192,200 year)
- College Station, TX (from $ 123,000 to $ 190,500 year)
The average salary range is between $ 114,126 and $ 191,048 year , with the average salary hovering around $ 145,794 year .
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Design Verification Engineer
Quix Recruitment Group LtdSan Francisco, CA, United States- Full-time
Our client is a world-leading technology company at the forefront of semiconductor innovation, powering some of the most advanced digital systems in the industry. Their work touches billions of users globally, driving next‑generation performance and efficiency across highly complex hardware and software ecosystems.
They are seeking a Design Verification Engineer with deep expertise in SystemVerilog / UVM and digital ASIC verification. This role is critical for ensuring robust, reusable verification environments, achieving high functional coverage, and supporting rapid innovation in complex hardware designs that operate at massive scale.
What You’ll Do
- Develop comprehensive Core Verification Plans based on unit micro‑architecture and design specifications.
- Architect and implement reusable verification environments using SystemVerilog / UVM.
- Create and execute constrained‑random and directed tests to achieve high functional and code coverage for core units.
- Analyze simulation results, debug complex failures, and collaborate with design teams to root‑cause and resolve issues.
- Develop and maintain scripts (Python / Perl) to automate verification flows and regression management.
- Support verification of digital systems using standard IP components and interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
- Act as a technical leader within verification teams, providing feedback to RTL designers and IP architects.
Requirements
Nice‑to‑Have Qualifications (Not required, but beneficial)
Why This Role Matters
This position is central to delivering high‑performance, reliable digital hardware at global scale. You will have the opportunity to shape verification strategies, implement reusable test environments, and contribute to cutting‑edge projects that power complex systems used by millions worldwide. This is an environment where technical expertise meets massive real‑world impact.
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