Verification engineer Jobs in Berkeley, CA

Role Overview

We are seeking a Design Verification Engineer to ensure the functional correctness, performance, and reliability of complex semiconductor designs such as ASICs, SoCs, GPUs, or CPUs. The role focuses on developing robust verification environments and validating RTL designs prior to tape-out.

Key Responsibilities

• Develop and execute functional verification plans for ASIC / SoC designs
• Build SystemVerilog / UVM-based verification environments
• Write and maintain testbenches, test cases, assertions, and coverage models
• Perform RTL debugging and work closely with design engineers to resolve issues
• Ensure verification completeness using functional and code coverage metrics
• Participate in design reviews, spec reviews, and tape-out readiness
• Support regression testing and automation
• Contribute to continuous improvement of verification methodologies and flows

Required Qualifications

o SystemVerilog

o UVM (Universal Verification Methodology)

o RTL (Verilog)

Common Job Title Variations